clash-lib-0.2.0.1: CAES Language for Synchronous Hardware - As a Library

Safe HaskellNone

CLaSH.Netlist.VHDL

Description

Generate VHDL for assorted Netlist datatypes

Synopsis

Documentation

genVHDL :: Component -> VHDLM (String, Doc)Source

Generate VHDL for a Netlist component

mkTyPackage :: [HWType] -> VHDLM DocSource

Generate a VHDL package containing type definitions for the given HWTypes

vhdlType :: HWType -> VHDLM DocSource

Convert a Netlist HWType to a VHDL type

vhdlTypeDefault :: HWType -> VHDLM DocSource

Convert a Netlist HWType to a default VHDL value for that type

vhdlTypeMark :: HWType -> VHDLM DocSource

Convert a Netlist HWType to the root of a VHDL type

inst :: Declaration -> VHDLM (Maybe Doc)Source

Turn a Netlist Declaration to a VHDL concurrent block

exprSource

Arguments

:: Bool

Enclose in parenthesis?

-> Expr

Expr to convert

-> VHDLM Doc 

Turn a Netlist expression into a VHDL expression