Clash.Explicit.DDR

We simulate DDR signal by using Signals which have exactly half the period (or double the speed) of our normal Signals.

The primitives in this module can be used to produce of consume DDR signals.

DDR signals are not meant to be used internally in a design, but only to communicate with the outside world.

In some cases hardware specific DDR IN registers can be inferred by synthesis tools from these generic primitives. But to be sure your design will synthesize to dedicated hardware resources use the functions from Clash.Intel.DDR or Clash.Xilinx.DDR.

Documentation

ddrIn

Arguments

:: (HasCallStack, NFDataX a, KnownConfiguration fast (DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow (DomainConfiguration slow (2 * fPeriod) edge reset init polarity))

=> Clock slow

clock

-> Reset slow

reset

-> Enable slow

-> (a, a, a)

reset values

-> Signal fast a

DDR input signal

-> Signal slow (a, a)

normal speed output pairs

DDR input primitive

Consumes a DDR input signal and produces a regular signal containing a pair of values.

>>> printX $ sampleN 5 $ ddrIn systemClockGen systemResetGen enableGen (-1,-2,-3) (fromList [0..10] :: Signal "Fast" Int)
[(-1,-2),(-1,-2),(-3,2),(3,4),(5,6)]

ddrOut

Arguments

:: (HasCallStack, NFDataX a, KnownConfiguration fast (DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow (DomainConfiguration slow (2 * fPeriod) edge reset init polarity))

=> Clock slow

-> Reset slow

-> Enable slow

-> a

reset value

-> Signal slow (a, a)

Normal speed input pairs

-> Signal fast a

DDR output signal

DDR output primitive

Produces a DDR output signal from a normal signal of pairs of input.

>>> sampleN 7 (ddrOut systemClockGen systemResetGen enableGen (-1) (fromList [(0,1),(2,3),(4,5)]) :: Signal "Fast" Int)
[-1,-1,-1,2,3,4,5]

Internal

ddrIn# :: forall a slow fast fPeriod polarity edge reset init. (HasCallStack, NFDataX a, KnownConfiguration fast (DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow (DomainConfiguration slow (2 * fPeriod) edge reset init polarity)) => Clock slow -> Reset slow -> Enable slow -> a -> a -> a -> Signal fast a -> Signal slow (a, a)

ddrOut# :: (HasCallStack, NFDataX a, KnownConfiguration fast (DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow (DomainConfiguration slow (2 * fPeriod) edge reset init polarity)) => Clock slow -> Reset slow -> Enable slow -> a -> Signal slow a -> Signal slow a -> Signal fast a