Clash.Intel.DDR

DDR primitives for Intel FPGAs using ALTDDIO primitives.

For general information about DDR primitives see Clash.Explicit.DDR.

Note that a reset is only available on certain devices, see ALTDDIO userguide for the specifics: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_altddio.pdf

Documentation

altddioIn

Arguments

:: (HasCallStack, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity), KnownNat m)

=> SSymbol deviceFamily

The FPGA family

For example this can be instantiated as follows:

SSymbol @"Cyclone IV GX"

-> Clock slow

clock

-> Reset slow

reset

-> Enable slow

Global enable

-> Signal fast (BitVector m)

DDR input signal

-> Signal slow (BitVector m, BitVector m)

normal speed output pairs

Intel specific variant of ddrIn implemented using the ALTDDIO_IN IP core.

Reset values are 0

altddioOut

Arguments

:: (HasCallStack, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity), KnownNat m)

=> SSymbol deviceFamily

The FPGA family

For example this can be instantiated as follows:

SSymbol @"Cyclone IV E"

-> Clock slow

clock

-> Reset slow

reset

-> Enable slow

Global enable

-> Signal slow (BitVector m, BitVector m)

normal speed input pair

-> Signal fast (BitVector m)

DDR output signal

Intel specific variant of ddrOut implemented using the ALTDDIO_OUT IP core.

Reset value is 0