Clash.Explicit.RAM

RAM primitives with a combinational read port.

RAM synchronized to an arbitrary clock

asyncRam

Arguments

:: (Enum addr, HasCallStack, KnownDomain wdom, KnownDomain rdom)

=> Clock wdom

Clock to which to synchronize the write port of the RAM

-> Clock rdom

Clock to which the read address signal, r, is synchronized to

-> Enable wdom

Global enable

-> SNat n

Size n of the RAM

-> Signal rdom addr

Read address r

-> Signal wdom (Maybe (addr, a))

(write address w, value to write)

-> Signal rdom a

Value of the RAM at address r

Create a RAM with space for n elements

• NB: Initial content of the RAM is undefined

Additional helpful information:

• See Clash.Explicit.BlockRam for more information on how to use a RAM.

asyncRamPow2

Arguments

:: forall wdom rdom n a. (KnownNat n, HasCallStack, KnownDomain wdom, KnownDomain rdom)

=> Clock wdom

Clock to which to synchronize the write port of the RAM

-> Clock rdom

Clock to which the read address signal, r, is synchronized

-> Enable wdom

Global enable

-> Signal rdom (Unsigned n)

Read address r

-> Signal wdom (Maybe (Unsigned n, a))

(write address w, value to write)

-> Signal rdom a

Value of the RAM at address r

Create a RAM with space for 2^n elements

• NB: Initial content of the RAM is undefined

Additional helpful information:

• See Clash.Prelude.BlockRam for more information on how to use a RAM.

Internal

asyncRam#

Arguments

:: (HasCallStack, KnownDomain wdom, KnownDomain rdom)

=> Clock wdom

Clock to which to synchronize the write port of the RAM

-> Clock rdom

Clock to which the read address signal, r, is synchronized

-> Enable wdom

Global enable

-> SNat n

Size n of the RAM

-> Signal rdom Int

Read address r

-> Signal wdom Bool

Write enable

-> Signal wdom Int

Write address w

-> Signal wdom a

Value to write (at address w)

-> Signal rdom a

Value of the RAM at address r

RAM primitive