hsverilog: Synthesizable Verilog DSL supporting for multiple clock and reset
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Versions [RSS] | 0.1.0 |
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Change log | ChangeLog.md |
Dependencies | base (>=4.6 && <5), containers, shakespeare, text, transformers [details] |
License | BSD-3-Clause |
Author | Junji Hashimoto |
Maintainer | junji.hashimoto@gmail.com |
Category | Hardware |
Bug tracker | https://github.com/junjihashimoto/hsverilog/issues |
Source repo | head: git clone https://github.com/junjihashimoto/hsverilog.git |
Uploaded | by junjihashimoto at 2015-02-19T23:59:58Z |
Distributions | NixOS:0.1.0 |
Reverse Dependencies | 1 direct, 0 indirect [details] |
Downloads | 1179 total (8 in the last 30 days) |
Rating | (no votes yet) [estimated by Bayesian average] |
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Status | Docs available [build log] Last success reported on 2015-05-20 [all 2 reports] |