verilog: Verilog preprocessor, parser, and AST.
A parser and supporting a small subset of Verilog. Intended for machine generated, synthesizable code.
Modules
- Data
- Data.BitVec
- Language
- Language.Verilog
- Language.Verilog.AST
- Language.Verilog.Parser
- Language.Verilog.Parser.Lex
- Language.Verilog.Parser.Parse
- Language.Verilog.Parser.Preprocess
- Language.Verilog.Parser.Tokens
- Language.Verilog
Downloads
- verilog-0.0.11.tar.gz [browse] (Cabal source package)
- Package description (as included in the package)
Maintainer's Corner
For package maintainers and hackage trustees
Candidates
- No Candidates
Versions [RSS] | 0.0.0, 0.0.1, 0.0.2, 0.0.4, 0.0.5, 0.0.6, 0.0.7, 0.0.8, 0.0.9, 0.0.10, 0.0.11 |
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Dependencies | array (>=0.4 && <5.0), base (>=4.0 && <5.0) [details] |
License | BSD-3-Clause |
Author | Tom Hawkins <tomahawkins@gmail.com> |
Maintainer | Tom Hawkins <tomahawkins@gmail.com> |
Category | Language, Hardware, Embedded |
Home page | http://github.com/tomahawkins/verilog |
Source repo | head: git clone git://github.com/tomahawkins/verilog.git |
Uploaded | by TomHawkins at 2015-03-26T18:06:06Z |
Distributions | |
Reverse Dependencies | 1 direct, 0 indirect [details] |
Downloads | 7810 total (14 in the last 30 days) |
Rating | (no votes yet) [estimated by Bayesian average] |
Your Rating | |
Status | Docs not available [build log] All reported builds failed as of 2016-12-10 [all 7 reports] |