Clash.Backend

Documentation

type ModName = String

data Usage

Is a type used for internal or external use

Constructors

Internal

Internal use

External Text

External use, field indicates the library name

class Backend state where

Minimal complete definition

initBackend, hdlKind, primDirs, name, extension, extractTypes, genHDL, mkTyPackage, hdlType, hdlTypeErrValue, hdlTypeMark, hdlRecSel, hdlSig, genStmt, inst, expr, iwWidth, toBV, fromBV, hdlSyn, mkIdentifier, extendIdentifier, setModName, setSrcSpan, getSrcSpan, blockDecl, unextend, addInclude, addLibraries, addImports

Methods

initBackend :: Int -> HdlSyn -> state

Initial state for state monad

hdlKind :: state -> HDL

What HDL is the backend generating

primDirs :: state -> IO [FilePath]

Location for the primitive definitions

name :: state -> String

Name of backend, used for directory to put output files in. Should be | constant function / ignore argument.

extension :: state -> String

File extension for target langauge

extractTypes :: state -> HashSet HWType

Get the set of types out of state

genHDL :: String -> SrcSpan -> Component -> Mon (State state) ((String, Doc), [(String, Doc)])

Generate HDL for a Netlist component

mkTyPackage :: String -> [HWType] -> Mon (State state) [(String, Doc)]

Generate a HDL package containing type definitions for the given HWTypes

hdlType :: Usage -> HWType -> Mon (State state) Doc

Convert a Netlist HWType to a target HDL type

hdlTypeErrValue :: HWType -> Mon (State state) Doc

Convert a Netlist HWType to an HDL error value for that type

hdlTypeMark :: HWType -> Mon (State state) Doc

Convert a Netlist HWType to the root of a target HDL type

hdlRecSel :: HWType -> Int -> Mon (State state) Doc

Create a record selector

hdlSig :: Text -> HWType -> Mon (State state) Doc

Create a signal declaration from an identifier (Text) and Netlist HWType

genStmt :: Bool -> State state Doc

Create a generative block statement marker

inst :: Declaration -> Mon (State state) (Maybe Doc)

Turn a Netlist Declaration to a HDL concurrent block

expr :: Bool -> Expr -> Mon (State state) Doc

Turn a Netlist expression into a HDL expression

iwWidth :: State state Int

Bit-width of IntWordInteger

toBV :: HWType -> Text -> Mon (State state) Doc

Convert to a bit-vector

fromBV :: HWType -> Text -> Mon (State state) Doc

Convert from a bit-vector

hdlSyn :: State state HdlSyn

Synthesis tool we're generating HDL for

mkIdentifier :: State state (IdType -> Identifier -> Identifier)

mkIdentifier

extendIdentifier :: State state (IdType -> Identifier -> Identifier -> Identifier)

mkIdentifier

setModName :: ModName -> state -> state

setModName

setSrcSpan :: SrcSpan -> State state ()

setSrcSpan

getSrcSpan :: State state SrcSpan

getSrcSpan

blockDecl :: Text -> [Declaration] -> Mon (State state) Doc

Block of declarations

unextend :: State state (Identifier -> Identifier)

unextend/unescape identifier

addInclude :: (String, Doc) -> State state ()

addLibraries :: [Text] -> State state ()

addImports :: [Text] -> State state ()

Instances

Backend VerilogState

Methods

initBackend :: Int -> HdlSyn -> VerilogState

hdlKind :: VerilogState -> HDL

primDirs :: VerilogState -> IO [FilePath]

name :: VerilogState -> String

extension :: VerilogState -> String

extractTypes :: VerilogState -> HashSet HWType

genHDL :: String -> SrcSpan -> Component -> Mon (State VerilogState) ((String, Doc), [(String, Doc)])

mkTyPackage :: String -> [HWType] -> Mon (State VerilogState) [(String, Doc)]

hdlType :: Usage -> HWType -> Mon (State VerilogState) Doc

hdlTypeErrValue :: HWType -> Mon (State VerilogState) Doc

hdlTypeMark :: HWType -> Mon (State VerilogState) Doc

hdlRecSel :: HWType -> Int -> Mon (State VerilogState) Doc

hdlSig :: Text -> HWType -> Mon (State VerilogState) Doc

genStmt :: Bool -> State VerilogState Doc

inst :: Declaration -> Mon (State VerilogState) (Maybe Doc)

expr :: Bool -> Expr -> Mon (State VerilogState) Doc

iwWidth :: State VerilogState Int

toBV :: HWType -> Text -> Mon (State VerilogState) Doc

fromBV :: HWType -> Text -> Mon (State VerilogState) Doc

hdlSyn :: State VerilogState HdlSyn

mkIdentifier :: State VerilogState (IdType -> Identifier -> Identifier)

extendIdentifier :: State VerilogState (IdType -> Identifier -> Identifier -> Identifier)

setModName :: ModName -> VerilogState -> VerilogState

setSrcSpan :: SrcSpan -> State VerilogState ()

getSrcSpan :: State VerilogState SrcSpan

blockDecl :: Text -> [Declaration] -> Mon (State VerilogState) Doc

unextend :: State VerilogState (Identifier -> Identifier)

addInclude :: (String, Doc) -> State VerilogState ()

addLibraries :: [Text] -> State VerilogState ()

addImports :: [Text] -> State VerilogState ()

Backend VHDLState

Methods

initBackend :: Int -> HdlSyn -> VHDLState

hdlKind :: VHDLState -> HDL

primDirs :: VHDLState -> IO [FilePath]

name :: VHDLState -> String

extension :: VHDLState -> String

extractTypes :: VHDLState -> HashSet HWType

genHDL :: String -> SrcSpan -> Component -> Mon (State VHDLState) ((String, Doc), [(String, Doc)])

mkTyPackage :: String -> [HWType] -> Mon (State VHDLState) [(String, Doc)]

hdlType :: Usage -> HWType -> Mon (State VHDLState) Doc

hdlTypeErrValue :: HWType -> Mon (State VHDLState) Doc

hdlTypeMark :: HWType -> Mon (State VHDLState) Doc

hdlRecSel :: HWType -> Int -> Mon (State VHDLState) Doc

hdlSig :: Text -> HWType -> Mon (State VHDLState) Doc

genStmt :: Bool -> State VHDLState Doc

inst :: Declaration -> Mon (State VHDLState) (Maybe Doc)

expr :: Bool -> Expr -> Mon (State VHDLState) Doc

iwWidth :: State VHDLState Int

toBV :: HWType -> Text -> Mon (State VHDLState) Doc

fromBV :: HWType -> Text -> Mon (State VHDLState) Doc

hdlSyn :: State VHDLState HdlSyn

mkIdentifier :: State VHDLState (IdType -> Identifier -> Identifier)

extendIdentifier :: State VHDLState (IdType -> Identifier -> Identifier -> Identifier)

setModName :: ModName -> VHDLState -> VHDLState

setSrcSpan :: SrcSpan -> State VHDLState ()

getSrcSpan :: State VHDLState SrcSpan

blockDecl :: Text -> [Declaration] -> Mon (State VHDLState) Doc

unextend :: State VHDLState (Identifier -> Identifier)

addInclude :: (String, Doc) -> State VHDLState ()

addLibraries :: [Text] -> State VHDLState ()

addImports :: [Text] -> State VHDLState ()

Backend SystemVerilogState

Methods

initBackend :: Int -> HdlSyn -> SystemVerilogState

hdlKind :: SystemVerilogState -> HDL

primDirs :: SystemVerilogState -> IO [FilePath]

name :: SystemVerilogState -> String

extension :: SystemVerilogState -> String

extractTypes :: SystemVerilogState -> HashSet HWType

genHDL :: String -> SrcSpan -> Component -> Mon (State SystemVerilogState) ((String, Doc), [(String, Doc)])

mkTyPackage :: String -> [HWType] -> Mon (State SystemVerilogState) [(String, Doc)]

hdlType :: Usage -> HWType -> Mon (State SystemVerilogState) Doc

hdlTypeErrValue :: HWType -> Mon (State SystemVerilogState) Doc

hdlTypeMark :: HWType -> Mon (State SystemVerilogState) Doc

hdlRecSel :: HWType -> Int -> Mon (State SystemVerilogState) Doc

hdlSig :: Text -> HWType -> Mon (State SystemVerilogState) Doc

genStmt :: Bool -> State SystemVerilogState Doc

inst :: Declaration -> Mon (State SystemVerilogState) (Maybe Doc)

expr :: Bool -> Expr -> Mon (State SystemVerilogState) Doc

iwWidth :: State SystemVerilogState Int

toBV :: HWType -> Text -> Mon (State SystemVerilogState) Doc

fromBV :: HWType -> Text -> Mon (State SystemVerilogState) Doc

hdlSyn :: State SystemVerilogState HdlSyn

mkIdentifier :: State SystemVerilogState (IdType -> Identifier -> Identifier)

extendIdentifier :: State SystemVerilogState (IdType -> Identifier -> Identifier -> Identifier)

setModName :: ModName -> SystemVerilogState -> SystemVerilogState

setSrcSpan :: SrcSpan -> State SystemVerilogState ()

getSrcSpan :: State SystemVerilogState SrcSpan

blockDecl :: Text -> [Declaration] -> Mon (State SystemVerilogState) Doc

unextend :: State SystemVerilogState (Identifier -> Identifier)

addInclude :: (String, Doc) -> State SystemVerilogState ()

addLibraries :: [Text] -> State SystemVerilogState ()

addImports :: [Text] -> State SystemVerilogState ()

nestM :: Modifier -> Modifier -> Maybe Modifier

Try to merge nested modifiers into a single modifier, needed by the VHDL and SystemVerilog backend.

escapeTemplate :: Identifier -> Identifier

Replace a normal HDL template placeholder with an unescaped/unextended template placeholder.

Needed when the the place-holder is filled with an escaped/extended identifier inside an escaped/extended identifier and we want to strip the escape /extension markers. Otherwise we end up with illegal identifiers.