Clash.Backend.SystemVerilog

Generate SystemVerilog for assorted Netlist datatypes

Documentation

data SystemVerilogState

State for the SystemVerilogM monad:

Instances

HasIdentifierSet SystemVerilogState

Defined in Clash.Backend.SystemVerilog

Methods

identifierSet :: Lens' SystemVerilogState IdentifierSet

Backend SystemVerilogState

Defined in Clash.Backend.SystemVerilog

Methods

initBackend :: Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> SystemVerilogState

hdlKind :: SystemVerilogState -> HDL

primDirs :: SystemVerilogState -> IO [FilePath]

name :: SystemVerilogState -> String

extension :: SystemVerilogState -> String

extractTypes :: SystemVerilogState -> HashSet HWType

genHDL :: ModName -> SrcSpan -> IdentifierSet -> Component -> Mon (State SystemVerilogState) ((String, Doc), [(String, Doc)])

mkTyPackage :: ModName -> [HWType] -> Mon (State SystemVerilogState) [(String, Doc)]

hdlType :: Usage -> HWType -> Mon (State SystemVerilogState) Doc

hdlHWTypeKind :: HWType -> State SystemVerilogState HWKind

hdlTypeErrValue :: HWType -> Mon (State SystemVerilogState) Doc

hdlTypeMark :: HWType -> Mon (State SystemVerilogState) Doc

hdlRecSel :: HWType -> Int -> Mon (State SystemVerilogState) Doc

hdlSig :: Text -> HWType -> Mon (State SystemVerilogState) Doc

genStmt :: Bool -> State SystemVerilogState Doc

inst :: Declaration -> Mon (State SystemVerilogState) (Maybe Doc)

expr :: Bool -> Expr -> Mon (State SystemVerilogState) Doc

iwWidth :: State SystemVerilogState Int

toBV :: HWType -> Text -> Mon (State SystemVerilogState) Doc

fromBV :: HWType -> Text -> Mon (State SystemVerilogState) Doc

hdlSyn :: State SystemVerilogState HdlSyn

setModName :: ModName -> SystemVerilogState -> SystemVerilogState

setSrcSpan :: SrcSpan -> State SystemVerilogState ()

getSrcSpan :: State SystemVerilogState SrcSpan

blockDecl :: Identifier -> [Declaration] -> Mon (State SystemVerilogState) Doc

addIncludes :: [(String, Doc)] -> State SystemVerilogState ()

addLibraries :: [Text] -> State SystemVerilogState ()

addImports :: [Text] -> State SystemVerilogState ()

addAndSetData :: FilePath -> State SystemVerilogState String

getDataFiles :: State SystemVerilogState [(String, FilePath)]

addMemoryDataFile :: (String, String) -> State SystemVerilogState ()

getMemoryDataFiles :: State SystemVerilogState [(String, String)]

ifThenElseExpr :: SystemVerilogState -> Bool

aggressiveXOptBB :: State SystemVerilogState AggressiveXOptBB