Clash.Backend

Documentation

primsRoot :: IO FilePath

clashVer :: String

type ModName = Text

data Usage

Is a type used for internal or external use

Constructors

Internal

Internal use

External Text

External use, field indicates the library name

newtype AggressiveXOptBB

Is '-fclash-aggresive-x-optimization-blackbox' set?

Constructors

AggressiveXOptBB Bool

data HWKind

Kind of a HDL type. Used to determine whether types need conversions in order to cross top entity boundaries.

Constructors

PrimitiveType

A type defined in an HDL spec. Usually types such as: bool, bit, ..

SynonymType

A user defined type that's simply a synonym for another type, very much like a type synonym in Haskell. As long as two synonym types refer to the same type, they can be used interchangeably. E.g., a subtype in VHDL.

UserType

User defined type that's not interchangeable with any others, even if the underlying structures are the same. Similar to an ADT in Haskell.

class HasIdentifierSet state => Backend state where

Methods

initBackend :: Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> state

Initial state for state monad

hdlKind :: state -> HDL

What HDL is the backend generating

primDirs :: state -> IO [FilePath]

Location for the primitive definitions

name :: state -> String

Name of backend, used for directory to put output files in. Should be constant function / ignore argument.

extension :: state -> String

File extension for target langauge

extractTypes :: state -> HashSet HWType

Get the set of types out of state

genHDL :: ModName -> SrcSpan -> IdentifierSet -> Component -> Mon (State state) ((String, Doc), [(String, Doc)])

Generate HDL for a Netlist component

mkTyPackage :: ModName -> [HWType] -> Mon (State state) [(String, Doc)]

Generate a HDL package containing type definitions for the given HWTypes

hdlType :: Usage -> HWType -> Mon (State state) Doc

Convert a Netlist HWType to a target HDL type

hdlHWTypeKind :: HWType -> State state HWKind

Query what kind of type a given HDL type is

hdlTypeErrValue :: HWType -> Mon (State state) Doc

Convert a Netlist HWType to an HDL error value for that type

hdlTypeMark :: HWType -> Mon (State state) Doc

Convert a Netlist HWType to the root of a target HDL type

hdlRecSel :: HWType -> Int -> Mon (State state) Doc

Create a record selector

hdlSig :: Text -> HWType -> Mon (State state) Doc

Create a signal declaration from an identifier (Text) and Netlist HWType

genStmt :: Bool -> State state Doc

Create a generative block statement marker

inst :: Declaration -> Mon (State state) (Maybe Doc)

Turn a Netlist Declaration to a HDL concurrent block

expr

Arguments

:: Bool

Enclose in parentheses?

-> Expr

Expr to convert

-> Mon (State state) Doc

Turn a Netlist expression into a HDL expression

iwWidth :: State state Int

Bit-width of Int,Word,Integer

toBV :: HWType -> Text -> Mon (State state) Doc

Convert to a bit-vector

fromBV :: HWType -> Text -> Mon (State state) Doc

Convert from a bit-vector

hdlSyn :: State state HdlSyn

Synthesis tool we're generating HDL for

setModName :: ModName -> state -> state

setModName

setSrcSpan :: SrcSpan -> State state ()

setSrcSpan

getSrcSpan :: State state SrcSpan

getSrcSpan

blockDecl :: Identifier -> [Declaration] -> Mon (State state) Doc

Block of declarations

addIncludes :: [(String, Doc)] -> State state ()

addLibraries :: [Text] -> State state ()

addImports :: [Text] -> State state ()

addAndSetData :: FilePath -> State state String

getDataFiles :: State state [(String, FilePath)]

addMemoryDataFile :: (String, String) -> State state ()

getMemoryDataFiles :: State state [(String, String)]

ifThenElseExpr :: state -> Bool

aggressiveXOptBB :: State state AggressiveXOptBB

Whether -fclash-aggressive-x-optimization-blackboxes was set

Instances

Backend VerilogState

Defined in Clash.Backend.Verilog

Methods

initBackend :: Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> VerilogState

hdlKind :: VerilogState -> HDL

primDirs :: VerilogState -> IO [FilePath]

name :: VerilogState -> String

extension :: VerilogState -> String

extractTypes :: VerilogState -> HashSet HWType

genHDL :: ModName -> SrcSpan -> IdentifierSet -> Component -> Mon (State VerilogState) ((String, Doc), [(String, Doc)])

mkTyPackage :: ModName -> [HWType] -> Mon (State VerilogState) [(String, Doc)]

hdlType :: Usage -> HWType -> Mon (State VerilogState) Doc

hdlHWTypeKind :: HWType -> State VerilogState HWKind

hdlTypeErrValue :: HWType -> Mon (State VerilogState) Doc

hdlTypeMark :: HWType -> Mon (State VerilogState) Doc

hdlRecSel :: HWType -> Int -> Mon (State VerilogState) Doc

hdlSig :: Text -> HWType -> Mon (State VerilogState) Doc

genStmt :: Bool -> State VerilogState Doc

inst :: Declaration -> Mon (State VerilogState) (Maybe Doc)

expr :: Bool -> Expr -> Mon (State VerilogState) Doc

iwWidth :: State VerilogState Int

toBV :: HWType -> Text -> Mon (State VerilogState) Doc

fromBV :: HWType -> Text -> Mon (State VerilogState) Doc

hdlSyn :: State VerilogState HdlSyn

setModName :: ModName -> VerilogState -> VerilogState

setSrcSpan :: SrcSpan -> State VerilogState ()

getSrcSpan :: State VerilogState SrcSpan

blockDecl :: Identifier -> [Declaration] -> Mon (State VerilogState) Doc

addIncludes :: [(String, Doc)] -> State VerilogState ()

addLibraries :: [Text] -> State VerilogState ()

addImports :: [Text] -> State VerilogState ()

addAndSetData :: FilePath -> State VerilogState String

getDataFiles :: State VerilogState [(String, FilePath)]

addMemoryDataFile :: (String, String) -> State VerilogState ()

getMemoryDataFiles :: State VerilogState [(String, String)]

ifThenElseExpr :: VerilogState -> Bool

aggressiveXOptBB :: State VerilogState AggressiveXOptBB

Backend VHDLState

Defined in Clash.Backend.VHDL

Methods

initBackend :: Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> VHDLState

hdlKind :: VHDLState -> HDL

primDirs :: VHDLState -> IO [FilePath]

name :: VHDLState -> String

extension :: VHDLState -> String

extractTypes :: VHDLState -> HashSet HWType

genHDL :: ModName -> SrcSpan -> IdentifierSet -> Component -> Mon (State VHDLState) ((String, Doc), [(String, Doc)])

mkTyPackage :: ModName -> [HWType] -> Mon (State VHDLState) [(String, Doc)]

hdlType :: Usage -> HWType -> Mon (State VHDLState) Doc

hdlHWTypeKind :: HWType -> State VHDLState HWKind

hdlTypeErrValue :: HWType -> Mon (State VHDLState) Doc

hdlTypeMark :: HWType -> Mon (State VHDLState) Doc

hdlRecSel :: HWType -> Int -> Mon (State VHDLState) Doc

hdlSig :: Text -> HWType -> Mon (State VHDLState) Doc

genStmt :: Bool -> State VHDLState Doc

inst :: Declaration -> Mon (State VHDLState) (Maybe Doc)

expr :: Bool -> Expr -> Mon (State VHDLState) Doc

iwWidth :: State VHDLState Int

toBV :: HWType -> Text -> Mon (State VHDLState) Doc

fromBV :: HWType -> Text -> Mon (State VHDLState) Doc

hdlSyn :: State VHDLState HdlSyn

setModName :: ModName -> VHDLState -> VHDLState

setSrcSpan :: SrcSpan -> State VHDLState ()

getSrcSpan :: State VHDLState SrcSpan

blockDecl :: Identifier -> [Declaration] -> Mon (State VHDLState) Doc

addIncludes :: [(String, Doc)] -> State VHDLState ()

addLibraries :: [Text] -> State VHDLState ()

addImports :: [Text] -> State VHDLState ()

addAndSetData :: FilePath -> State VHDLState String

getDataFiles :: State VHDLState [(String, FilePath)]

addMemoryDataFile :: (String, String) -> State VHDLState ()

getMemoryDataFiles :: State VHDLState [(String, String)]

ifThenElseExpr :: VHDLState -> Bool

aggressiveXOptBB :: State VHDLState AggressiveXOptBB

Backend SystemVerilogState

Defined in Clash.Backend.SystemVerilog

Methods

initBackend :: Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> SystemVerilogState

hdlKind :: SystemVerilogState -> HDL

primDirs :: SystemVerilogState -> IO [FilePath]

name :: SystemVerilogState -> String

extension :: SystemVerilogState -> String

extractTypes :: SystemVerilogState -> HashSet HWType

genHDL :: ModName -> SrcSpan -> IdentifierSet -> Component -> Mon (State SystemVerilogState) ((String, Doc), [(String, Doc)])

mkTyPackage :: ModName -> [HWType] -> Mon (State SystemVerilogState) [(String, Doc)]

hdlType :: Usage -> HWType -> Mon (State SystemVerilogState) Doc

hdlHWTypeKind :: HWType -> State SystemVerilogState HWKind

hdlTypeErrValue :: HWType -> Mon (State SystemVerilogState) Doc

hdlTypeMark :: HWType -> Mon (State SystemVerilogState) Doc

hdlRecSel :: HWType -> Int -> Mon (State SystemVerilogState) Doc

hdlSig :: Text -> HWType -> Mon (State SystemVerilogState) Doc

genStmt :: Bool -> State SystemVerilogState Doc

inst :: Declaration -> Mon (State SystemVerilogState) (Maybe Doc)

expr :: Bool -> Expr -> Mon (State SystemVerilogState) Doc

iwWidth :: State SystemVerilogState Int

toBV :: HWType -> Text -> Mon (State SystemVerilogState) Doc

fromBV :: HWType -> Text -> Mon (State SystemVerilogState) Doc

hdlSyn :: State SystemVerilogState HdlSyn

setModName :: ModName -> SystemVerilogState -> SystemVerilogState

setSrcSpan :: SrcSpan -> State SystemVerilogState ()

getSrcSpan :: State SystemVerilogState SrcSpan

blockDecl :: Identifier -> [Declaration] -> Mon (State SystemVerilogState) Doc

addIncludes :: [(String, Doc)] -> State SystemVerilogState ()

addLibraries :: [Text] -> State SystemVerilogState ()

addImports :: [Text] -> State SystemVerilogState ()

addAndSetData :: FilePath -> State SystemVerilogState String

getDataFiles :: State SystemVerilogState [(String, FilePath)]

addMemoryDataFile :: (String, String) -> State SystemVerilogState ()

getMemoryDataFiles :: State SystemVerilogState [(String, String)]

ifThenElseExpr :: SystemVerilogState -> Bool

aggressiveXOptBB :: State SystemVerilogState AggressiveXOptBB