Clash.Backend

Documentation

primsRoot :: IO FilePath

clashVer :: String

type ModName = Text

data Usage

Is a type used for internal or external use

Constructors

Internal

Internal use

External Text

External use, field indicates the library name

newtype AggressiveXOptBB

Is '-fclash-aggresive-x-optimization-blackbox' set?

Constructors

AggressiveXOptBB Bool

newtype RenderEnums

Is '-fclash-render-enums' set?

Constructors

RenderEnums Bool

data HWKind

Kind of a HDL type. Used to determine whether types need conversions in order to cross top entity boundaries.

Constructors

PrimitiveType

A type defined in an HDL spec. Usually types such as: bool, bit, ..

SynonymType

A user defined type that's simply a synonym for another type, very much like a type synonym in Haskell. As long as two synonym types refer to the same type, they can be used interchangeably. E.g., a subtype in VHDL.

UserType

User defined type that's not interchangeable with any others, even if the underlying structures are the same. Similar to an ADT in Haskell.

type DomainMap = HashMap Text VDomainConfiguration

emptyDomainMap :: DomainMap

class HasIdentifierSet state => Backend state where

Methods

initBackend :: ClashOpts -> state

Initial state for state monad

hdlKind :: state -> HDL

What HDL is the backend generating

primDirs :: state -> IO [FilePath]

Location for the primitive definitions

name :: state -> String

Name of backend, used for directory to put output files in. Should be constant function / ignore argument.

extension :: state -> String

File extension for target langauge

extractTypes :: state -> HashSet HWType

Get the set of types out of state

genHDL :: ModName -> SrcSpan -> IdentifierSet -> Component -> Ap (State state) ((String, Doc), [(String, Doc)])

Generate HDL for a Netlist component

mkTyPackage :: ModName -> [HWType] -> Ap (State state) [(String, Doc)]

Generate a HDL package containing type definitions for the given HWTypes

hdlType :: Usage -> HWType -> Ap (State state) Doc

Convert a Netlist HWType to a target HDL type

hdlHWTypeKind :: HWType -> State state HWKind

Query what kind of type a given HDL type is

hdlTypeErrValue :: HWType -> Ap (State state) Doc

Convert a Netlist HWType to an HDL error value for that type

hdlTypeMark :: HWType -> Ap (State state) Doc

Convert a Netlist HWType to the root of a target HDL type

hdlRecSel :: HWType -> Int -> Ap (State state) Doc

Create a record selector

hdlSig :: Text -> HWType -> Ap (State state) Doc

Create a signal declaration from an identifier (Text) and Netlist HWType

genStmt :: Bool -> State state Doc

Create a generative block statement marker

inst :: Declaration -> Ap (State state) (Maybe Doc)

Turn a Netlist Declaration to a HDL concurrent block

expr

Arguments

:: Bool

Enclose in parentheses?

-> Expr

Expr to convert

-> Ap (State state) Doc

Turn a Netlist expression into a HDL expression

iwWidth :: State state Int

Bit-width of Int,Word,Integer

toBV :: HWType -> Text -> Ap (State state) Doc

Convert to a bit-vector

fromBV :: HWType -> Text -> Ap (State state) Doc

Convert from a bit-vector

hdlSyn :: State state HdlSyn

Synthesis tool we're generating HDL for

setModName :: ModName -> state -> state

setModName

setTopName :: Identifier -> state -> state

Set the name of the current top entity

getTopName :: State state Identifier

Get the name of the current top entity

setSrcSpan :: SrcSpan -> State state ()

setSrcSpan

getSrcSpan :: State state SrcSpan

getSrcSpan

blockDecl :: Identifier -> [Declaration] -> Ap (State state) Doc

Block of declarations

addIncludes :: [(String, Doc)] -> State state ()

addLibraries :: [Text] -> State state ()

addImports :: [Text] -> State state ()

addAndSetData :: FilePath -> State state String

getDataFiles :: State state [(String, FilePath)]

addMemoryDataFile :: (String, String) -> State state ()

getMemoryDataFiles :: State state [(String, String)]

ifThenElseExpr :: state -> Bool

aggressiveXOptBB :: State state AggressiveXOptBB

Whether -fclash-aggressive-x-optimization-blackboxes was set

renderEnums :: State state RenderEnums

Whether -fclash-no-render-enums was set

domainConfigurations :: State state DomainMap

All the domain configurations of design

setDomainConfigurations :: DomainMap -> state -> state

Set the domain configurations

Instances

Backend VerilogState

Defined in Clash.Backend.Verilog

Methods

initBackend :: ClashOpts -> VerilogState

hdlKind :: VerilogState -> HDL

primDirs :: VerilogState -> IO [FilePath]

name :: VerilogState -> String

extension :: VerilogState -> String

extractTypes :: VerilogState -> HashSet HWType

genHDL :: ModName -> SrcSpan -> IdentifierSet -> Component -> Ap (State VerilogState) ((String, Doc), [(String, Doc)])

mkTyPackage :: ModName -> [HWType] -> Ap (State VerilogState) [(String, Doc)]

hdlType :: Usage -> HWType -> Ap (State VerilogState) Doc

hdlHWTypeKind :: HWType -> State VerilogState HWKind

hdlTypeErrValue :: HWType -> Ap (State VerilogState) Doc

hdlTypeMark :: HWType -> Ap (State VerilogState) Doc

hdlRecSel :: HWType -> Int -> Ap (State VerilogState) Doc

hdlSig :: Text -> HWType -> Ap (State VerilogState) Doc

genStmt :: Bool -> State VerilogState Doc

inst :: Declaration -> Ap (State VerilogState) (Maybe Doc)

expr :: Bool -> Expr -> Ap (State VerilogState) Doc

iwWidth :: State VerilogState Int

toBV :: HWType -> Text -> Ap (State VerilogState) Doc

fromBV :: HWType -> Text -> Ap (State VerilogState) Doc

hdlSyn :: State VerilogState HdlSyn

setModName :: ModName -> VerilogState -> VerilogState

setTopName :: Identifier -> VerilogState -> VerilogState

getTopName :: State VerilogState Identifier

setSrcSpan :: SrcSpan -> State VerilogState ()

getSrcSpan :: State VerilogState SrcSpan

blockDecl :: Identifier -> [Declaration] -> Ap (State VerilogState) Doc

addIncludes :: [(String, Doc)] -> State VerilogState ()

addLibraries :: [Text] -> State VerilogState ()

addImports :: [Text] -> State VerilogState ()

addAndSetData :: FilePath -> State VerilogState String

getDataFiles :: State VerilogState [(String, FilePath)]

addMemoryDataFile :: (String, String) -> State VerilogState ()

getMemoryDataFiles :: State VerilogState [(String, String)]

ifThenElseExpr :: VerilogState -> Bool

aggressiveXOptBB :: State VerilogState AggressiveXOptBB

renderEnums :: State VerilogState RenderEnums

domainConfigurations :: State VerilogState DomainMap

setDomainConfigurations :: DomainMap -> VerilogState -> VerilogState

Backend VHDLState

Defined in Clash.Backend.VHDL

Methods

initBackend :: ClashOpts -> VHDLState

hdlKind :: VHDLState -> HDL

primDirs :: VHDLState -> IO [FilePath]

name :: VHDLState -> String

extension :: VHDLState -> String

extractTypes :: VHDLState -> HashSet HWType

genHDL :: ModName -> SrcSpan -> IdentifierSet -> Component -> Ap (State VHDLState) ((String, Doc), [(String, Doc)])

mkTyPackage :: ModName -> [HWType] -> Ap (State VHDLState) [(String, Doc)]

hdlType :: Usage -> HWType -> Ap (State VHDLState) Doc

hdlHWTypeKind :: HWType -> State VHDLState HWKind

hdlTypeErrValue :: HWType -> Ap (State VHDLState) Doc

hdlTypeMark :: HWType -> Ap (State VHDLState) Doc

hdlRecSel :: HWType -> Int -> Ap (State VHDLState) Doc

hdlSig :: Text -> HWType -> Ap (State VHDLState) Doc

genStmt :: Bool -> State VHDLState Doc

inst :: Declaration -> Ap (State VHDLState) (Maybe Doc)

expr :: Bool -> Expr -> Ap (State VHDLState) Doc

iwWidth :: State VHDLState Int

toBV :: HWType -> Text -> Ap (State VHDLState) Doc

fromBV :: HWType -> Text -> Ap (State VHDLState) Doc

hdlSyn :: State VHDLState HdlSyn

setModName :: ModName -> VHDLState -> VHDLState

setTopName :: Identifier -> VHDLState -> VHDLState

getTopName :: State VHDLState Identifier

setSrcSpan :: SrcSpan -> State VHDLState ()

getSrcSpan :: State VHDLState SrcSpan

blockDecl :: Identifier -> [Declaration] -> Ap (State VHDLState) Doc

addIncludes :: [(String, Doc)] -> State VHDLState ()

addLibraries :: [Text] -> State VHDLState ()

addImports :: [Text] -> State VHDLState ()

addAndSetData :: FilePath -> State VHDLState String

getDataFiles :: State VHDLState [(String, FilePath)]

addMemoryDataFile :: (String, String) -> State VHDLState ()

getMemoryDataFiles :: State VHDLState [(String, String)]

ifThenElseExpr :: VHDLState -> Bool

aggressiveXOptBB :: State VHDLState AggressiveXOptBB

renderEnums :: State VHDLState RenderEnums

domainConfigurations :: State VHDLState DomainMap

setDomainConfigurations :: DomainMap -> VHDLState -> VHDLState

Backend SystemVerilogState

Defined in Clash.Backend.SystemVerilog

Methods

initBackend :: ClashOpts -> SystemVerilogState

hdlKind :: SystemVerilogState -> HDL

primDirs :: SystemVerilogState -> IO [FilePath]

name :: SystemVerilogState -> String

extension :: SystemVerilogState -> String

extractTypes :: SystemVerilogState -> HashSet HWType

genHDL :: ModName -> SrcSpan -> IdentifierSet -> Component -> Ap (State SystemVerilogState) ((String, Doc), [(String, Doc)])

mkTyPackage :: ModName -> [HWType] -> Ap (State SystemVerilogState) [(String, Doc)]

hdlType :: Usage -> HWType -> Ap (State SystemVerilogState) Doc

hdlHWTypeKind :: HWType -> State SystemVerilogState HWKind

hdlTypeErrValue :: HWType -> Ap (State SystemVerilogState) Doc

hdlTypeMark :: HWType -> Ap (State SystemVerilogState) Doc

hdlRecSel :: HWType -> Int -> Ap (State SystemVerilogState) Doc

hdlSig :: Text -> HWType -> Ap (State SystemVerilogState) Doc

genStmt :: Bool -> State SystemVerilogState Doc

inst :: Declaration -> Ap (State SystemVerilogState) (Maybe Doc)

expr :: Bool -> Expr -> Ap (State SystemVerilogState) Doc

iwWidth :: State SystemVerilogState Int

toBV :: HWType -> Text -> Ap (State SystemVerilogState) Doc

fromBV :: HWType -> Text -> Ap (State SystemVerilogState) Doc

hdlSyn :: State SystemVerilogState HdlSyn

setModName :: ModName -> SystemVerilogState -> SystemVerilogState

setTopName :: Identifier -> SystemVerilogState -> SystemVerilogState

getTopName :: State SystemVerilogState Identifier

setSrcSpan :: SrcSpan -> State SystemVerilogState ()

getSrcSpan :: State SystemVerilogState SrcSpan

blockDecl :: Identifier -> [Declaration] -> Ap (State SystemVerilogState) Doc

addIncludes :: [(String, Doc)] -> State SystemVerilogState ()

addLibraries :: [Text] -> State SystemVerilogState ()

addImports :: [Text] -> State SystemVerilogState ()

addAndSetData :: FilePath -> State SystemVerilogState String

getDataFiles :: State SystemVerilogState [(String, FilePath)]

addMemoryDataFile :: (String, String) -> State SystemVerilogState ()

getMemoryDataFiles :: State SystemVerilogState [(String, String)]

ifThenElseExpr :: SystemVerilogState -> Bool

aggressiveXOptBB :: State SystemVerilogState AggressiveXOptBB

renderEnums :: State SystemVerilogState RenderEnums

domainConfigurations :: State SystemVerilogState DomainMap

setDomainConfigurations :: DomainMap -> SystemVerilogState -> SystemVerilogState