{-# LANGUAGE DataKinds #-}
{-# LANGUAGE FlexibleContexts #-}
{-# LANGUAGE TypeFamilies #-}
{-# LANGUAGE ScopedTypeVariables #-}
{-# LANGUAGE Unsafe #-}
{-# OPTIONS_HADDOCK show-extensions #-}
module Clash.Prelude.Testbench
(
assert
, ignoreFor
, outputVerifier'
, outputVerifierBitVector'
, stimuliGenerator
, E.tbClockGen
, E.tbEnableGen
, E.tbSystemClockGen
)
where
import GHC.TypeLits (KnownNat)
import qualified Clash.Explicit.Testbench as E
import Clash.Signal
(HiddenClock, HiddenReset, HiddenClockResetEnable, Signal,
DomainResetKind, ResetKind(Asynchronous), hideClock, hideReset, hideClockResetEnable)
import Clash.Promoted.Nat (SNat)
import Clash.Sized.BitVector (BitVector)
import Clash.Sized.Vector (Vec)
import Clash.XException (ShowX)
assert
:: (Eq a, ShowX a, HiddenClock dom , HiddenReset dom )
=> String
-> Signal dom a
-> Signal dom a
-> Signal dom b
-> Signal dom b
assert :: String
-> Signal dom a -> Signal dom a -> Signal dom b -> Signal dom b
assert msg :: String
msg actual :: Signal dom a
actual expected :: Signal dom a
expected ret :: Signal dom b
ret =
(Reset dom
-> String
-> Signal dom a
-> Signal dom a
-> Signal dom b
-> Signal dom b)
-> String
-> Signal dom a
-> Signal dom a
-> Signal dom b
-> Signal dom b
forall (dom :: Domain) r. HiddenReset dom => (Reset dom -> r) -> r
hideReset ((Clock dom
-> Reset dom
-> String
-> Signal dom a
-> Signal dom a
-> Signal dom b
-> Signal dom b)
-> Reset dom
-> String
-> Signal dom a
-> Signal dom a
-> Signal dom b
-> Signal dom b
forall (dom :: Domain) r. HiddenClock dom => (Clock dom -> r) -> r
hideClock Clock dom
-> Reset dom
-> String
-> Signal dom a
-> Signal dom a
-> Signal dom b
-> Signal dom b
forall (dom :: Domain) a b.
(KnownDomain dom, Eq a, ShowX a) =>
Clock dom
-> Reset dom
-> String
-> Signal dom a
-> Signal dom a
-> Signal dom b
-> Signal dom b
E.assert) String
msg Signal dom a
actual Signal dom a
expected Signal dom b
ret
{-# INLINE assert #-}
stimuliGenerator
:: ( KnownNat l
, HiddenClock dom
, HiddenReset dom )
=> Vec l a
-> Signal dom a
stimuliGenerator :: Vec l a -> Signal dom a
stimuliGenerator = (Reset dom -> Vec l a -> Signal dom a) -> Vec l a -> Signal dom a
forall (dom :: Domain) r. HiddenReset dom => (Reset dom -> r) -> r
hideReset ((Clock dom -> Reset dom -> Vec l a -> Signal dom a)
-> Reset dom -> Vec l a -> Signal dom a
forall (dom :: Domain) r. HiddenClock dom => (Clock dom -> r) -> r
hideClock Clock dom -> Reset dom -> Vec l a -> Signal dom a
forall (l :: Nat) (dom :: Domain) a.
(KnownNat l, KnownDomain dom) =>
Clock dom -> Reset dom -> Vec l a -> Signal dom a
E.stimuliGenerator)
{-# INLINE stimuliGenerator #-}
outputVerifier'
:: ( KnownNat l
, Eq a
, ShowX a
, DomainResetKind dom ~ 'Asynchronous
, HiddenClock dom
, HiddenReset dom )
=> Vec l a
-> Signal dom a
-> Signal dom Bool
outputVerifier' :: Vec l a -> Signal dom a -> Signal dom Bool
outputVerifier' = (Reset dom -> Vec l a -> Signal dom a -> Signal dom Bool)
-> Vec l a -> Signal dom a -> Signal dom Bool
forall (dom :: Domain) r. HiddenReset dom => (Reset dom -> r) -> r
hideReset ((Clock dom
-> Reset dom -> Vec l a -> Signal dom a -> Signal dom Bool)
-> Reset dom -> Vec l a -> Signal dom a -> Signal dom Bool
forall (dom :: Domain) r. HiddenClock dom => (Clock dom -> r) -> r
hideClock Clock dom
-> Reset dom -> Vec l a -> Signal dom a -> Signal dom Bool
forall (l :: Nat) a (dom :: Domain).
(KnownNat l, KnownDomain dom, DomainResetKind dom ~ 'Asynchronous,
Eq a, ShowX a) =>
Clock dom
-> Reset dom -> Vec l a -> Signal dom a -> Signal dom Bool
E.outputVerifier')
{-# INLINE outputVerifier' #-}
outputVerifierBitVector'
:: ( KnownNat l
, KnownNat n
, DomainResetKind dom ~ 'Asynchronous
, HiddenClock dom
, HiddenReset dom )
=> Vec l (BitVector n)
-> Signal dom (BitVector n)
-> Signal dom Bool
outputVerifierBitVector' :: Vec l (BitVector n) -> Signal dom (BitVector n) -> Signal dom Bool
outputVerifierBitVector' = (Reset dom
-> Vec l (BitVector n)
-> Signal dom (BitVector n)
-> Signal dom Bool)
-> Vec l (BitVector n)
-> Signal dom (BitVector n)
-> Signal dom Bool
forall (dom :: Domain) r. HiddenReset dom => (Reset dom -> r) -> r
hideReset ((Clock dom
-> Reset dom
-> Vec l (BitVector n)
-> Signal dom (BitVector n)
-> Signal dom Bool)
-> Reset dom
-> Vec l (BitVector n)
-> Signal dom (BitVector n)
-> Signal dom Bool
forall (dom :: Domain) r. HiddenClock dom => (Clock dom -> r) -> r
hideClock Clock dom
-> Reset dom
-> Vec l (BitVector n)
-> Signal dom (BitVector n)
-> Signal dom Bool
forall (l :: Nat) (n :: Nat) (dom :: Domain).
(KnownNat l, KnownNat n, KnownDomain dom,
DomainResetKind dom ~ 'Asynchronous) =>
Clock dom
-> Reset dom
-> Vec l (BitVector n)
-> Signal dom (BitVector n)
-> Signal dom Bool
E.outputVerifierBitVector')
{-# INLINE outputVerifierBitVector' #-}
ignoreFor
:: HiddenClockResetEnable dom
=> SNat n
-> a
-> Signal dom a
-> Signal dom a
ignoreFor :: SNat n -> a -> Signal dom a -> Signal dom a
ignoreFor = (KnownDomain dom =>
Clock dom
-> Reset dom
-> Enable dom
-> SNat n
-> a
-> Signal dom a
-> Signal dom a)
-> SNat n -> a -> Signal dom a -> Signal dom a
forall (dom :: Domain) r.
HiddenClockResetEnable dom =>
(KnownDomain dom => Clock dom -> Reset dom -> Enable dom -> r) -> r
hideClockResetEnable KnownDomain dom =>
Clock dom
-> Reset dom
-> Enable dom
-> SNat n
-> a
-> Signal dom a
-> Signal dom a
forall (dom :: Domain) (n :: Nat) a.
KnownDomain dom =>
Clock dom
-> Reset dom
-> Enable dom
-> SNat n
-> a
-> Signal dom a
-> Signal dom a
E.ignoreFor
{-# INLINE ignoreFor #-}