Hardware.SiClock

This is the main API.

Documentation

type Frequency = Rational

type Divider = Rational

data Config

Constructors

Config

Fields

• _I2CDevice :: FilePath
• _I2CAddress :: Word8
• _XtalFrequency :: Frequency
• _maxPLLFrequency :: Frequency

Instances

Eq Config

Methods

(==) :: Config -> Config -> Bool

(/=) :: Config -> Config -> Bool

Show Config

Methods

showsPrec :: Int -> Config -> ShowS

show :: Config -> String

showList :: [Config] -> ShowS

defaultConfig :: Config

The defaultConfig if no environment variables are set.

defaultConfigEnv :: HasCallStack => IO Config

Check that defaultConfigEnv matches your hardware before you use it. Do not run any SiPLL code on a wrong i2c-bus, i.e. an internal I2C bus of your PC. (it might confuse and or wreck) your hardware. You can overwrite config values with the following ENV variables: SI_CLOCK_I2C_DEVICE SI_CLOCK_I2C_ADDRESS SI_CLOCK_XTAL_FREQUENCY SI_CLOCK_MAX_PLL_FREQUENCY

testIO :: IO ()

Quick test for the I2C connection (with default config).

type Synth a = forall m. MonadIO m => SynthT Config m a

runSynth :: HasCallStack => SynthT Config IO a -> IO a

Run the Synth monad with the config from defaultConfigEnv. | .i.e. reading Env

runSynthWith :: HasCallStack => Config -> SynthT Config IO a -> IO a

Run the Synth monad with a custom configuration.

askXtalFrequency :: Synth Frequency

askMaxPLLFrequency :: Synth Frequency

data PLL

An IC has PLL_A and PLL_B.

Constructors

PLL_A

PLL_B

Instances

Eq PLL

Methods

(==) :: PLL -> PLL -> Bool

(/=) :: PLL -> PLL -> Bool

Show PLL

Methods

showsPrec :: Int -> PLL -> ShowS

show :: PLL -> String

showList :: [PLL] -> ShowS

DividerAddr PLL

Address of a PLL divider.

Methods

toDividerAddr :: PLL -> Word8

data CLK

An IC has up to 8 clocks. (CLK_0..CLK_7).

Constructors

CLK_0

CLK_1

CLK_2

CLK_3

CLK_4

CLK_5

CLK_6

CLK_7

Instances

Enum CLK

Methods

succ :: CLK -> CLK

pred :: CLK -> CLK

toEnum :: Int -> CLK

fromEnum :: CLK -> Int

enumFrom :: CLK -> [CLK]

enumFromThen :: CLK -> CLK -> [CLK]

enumFromTo :: CLK -> CLK -> [CLK]

enumFromThenTo :: CLK -> CLK -> CLK -> [CLK]

Eq CLK

Methods

(==) :: CLK -> CLK -> Bool

(/=) :: CLK -> CLK -> Bool

Ord CLK

Methods

compare :: CLK -> CLK -> Ordering

(<) :: CLK -> CLK -> Bool

(<=) :: CLK -> CLK -> Bool

(>) :: CLK -> CLK -> Bool

(>=) :: CLK -> CLK -> Bool

max :: CLK -> CLK -> CLK

min :: CLK -> CLK -> CLK

Show CLK

Methods

showsPrec :: Int -> CLK -> ShowS

show :: CLK -> String

showList :: [CLK] -> ShowS

DividerAddr CLK

Address of a Clock divider.

Methods

toDividerAddr :: CLK -> Word8

pllReset :: Synth ()

Reset (both?) PLLs

clk0_On :: Synth ()

Turn on CLK_0 output.

clk0_Off :: Synth ()

Turn off CLK_0 output.

data DividerPair

Constructors

DividerPair

Fields

• _pllDivider :: Divider
• _clkDivider :: Divider

Instances

Show DividerPair

Methods

showsPrec :: Int -> DividerPair -> ShowS

show :: DividerPair -> String

showList :: [DividerPair] -> ShowS

setDividers :: PLL -> CLK -> Frequency -> Synth DividerPair

Set PLL and Clock dividers for a frequency.

defaultDividers :: Frequency -> Synth DividerPair

Compute a pair of good default pll and clk dividers. (clk divider is an integer)

setPLLDivider :: PLL -> Divider -> Synth ()

Set a PLL fractional divider

setPLLDivider_A :: Divider -> Synth ()

Short for setPLLDivider PLL_A

setPLLDivider_B :: Divider -> Synth ()

Short for setPLLDivider PLL_B

setCLKDivider :: CLK -> Word8 -> Divider -> Synth ()

Setup a Clock divider. The rfield is passed as a plain Word8. (ToDo high level API for rfields).

data CLK_Control_bits

Bits in the clock control registers.

Constructors

CLK_on

CLK_off

CLK_fractional

CLK_integer

CLK_multiPLLA

CLK_multiPLLB

CLK_inverted

CLK_XTAL

CLK_CLKin

CLK_multi

CLK_DRV2

CLK_DRV4

CLK_DRV6

CLK_DRV8

Instances

Eq CLK_Control_bits

Methods

(==) :: CLK_Control_bits -> CLK_Control_bits -> Bool

(/=) :: CLK_Control_bits -> CLK_Control_bits -> Bool

Show CLK_Control_bits

Methods

showsPrec :: Int -> CLK_Control_bits -> ShowS

show :: CLK_Control_bits -> String

showList :: [CLK_Control_bits] -> ShowS

setCLKControl :: CLK -> [CLK_Control_bits] -> Synth ()

setCLKControlRaw :: CLK -> Word8 -> Synth ()

controlBitsToWord8 :: [CLK_Control_bits] -> Word8

newtype DividerConf

A DividerConf is basically the bytestring that configures a fractional divider.

Constructors

DividerConf

Fields

• unDividerConf :: ByteString

Instances

Eq DividerConf

Methods

(==) :: DividerConf -> DividerConf -> Bool

(/=) :: DividerConf -> DividerConf -> Bool

Show DividerConf

Methods

showsPrec :: Int -> DividerConf -> ShowS

show :: DividerConf -> String

showList :: [DividerConf] -> ShowS

toDividerConf :: Word8 -> Divider -> DividerConf

Mangle a Divider and a rval into a DividerConf. This can be used to pre-compute all the math and to get the bits that define a divider.

setDividerRaw :: DividerAddr hw => hw -> DividerConf -> Synth ()

Setup some fractional divider with a pre-computed config. Using a pre-computed config might be faster or more convenient.

class DividerAddr a where

Get address of the fractional divider.

Minimal complete definition

toDividerAddr

Methods

toDividerAddr :: a -> Word8

Instances

DividerAddr Word8

Generic Address of fractional divider.

Methods

toDividerAddr :: Word8 -> Word8

DividerAddr CLK

Address of a Clock divider.

Methods

toDividerAddr :: CLK -> Word8

DividerAddr PLL

Address of a PLL divider.

Methods

toDividerAddr :: PLL -> Word8

_SI_CLK0_CONTROL :: Word8

_SI_CLK1_CONTROL :: Word8

_SI_CLK2_CONTROL :: Word8

_SI_SYNTH_PLL_A :: Word8

_SI_SYNTH_PLL_B :: Word8

_SI_PLL_RESET :: Word8

_SI_CLOCK_I2C_DEVICE :: String

_SI_CLOCK_I2C_ADDRESS :: String

_SI_CLOCK_XTAL_FREQUENCY :: String

_SI_CLOCK_MAX_PLL_FREQUENCY :: String