{-# LANGUAGE CPP #-}
{-# LANGUAGE FlexibleContexts #-}
{-# LANGUAGE TypeFamilies #-}
{-# LANGUAGE Safe #-}
{-# OPTIONS_HADDOCK show-extensions #-}
module Clash.Prelude.RAM
(
asyncRam
, asyncRamPow2
)
where
import GHC.TypeLits (KnownNat)
import GHC.Stack (HasCallStack, withFrozenCallStack)
import qualified Clash.Explicit.RAM as E
import Clash.Promoted.Nat (SNat)
import Clash.Signal
import Clash.Sized.Unsigned (Unsigned)
asyncRam
:: ( Enum addr
, HiddenClock dom
, HiddenEnable dom
, HasCallStack
)
=> SNat n
-> Signal dom addr
-> Signal dom (Maybe (addr, a))
-> Signal dom a
asyncRam = \sz rd wrM -> withFrozenCallStack
(hideEnable (\en -> hideClock (\clk -> E.asyncRam clk clk en sz rd wrM)))
{-# INLINE asyncRam #-}
asyncRamPow2
:: ( KnownNat n
, HiddenClock dom
, HiddenEnable dom
, HasCallStack )
=> Signal dom (Unsigned n)
-> Signal dom (Maybe (Unsigned n, a))
-> Signal dom a
asyncRamPow2 = \rd wrM -> withFrozenCallStack
(hideEnable (\en -> (hideClock (\clk -> E.asyncRamPow2 clk clk en rd wrM))))
{-# INLINE asyncRamPow2 #-}